1. Field of the Invention
The present invention relates to a technology for supporting (aiding) designing a circuit in which a Programmable Logic Device (PLD) is used as a component.
2. Description of the Related Art
In a circuit design CAD, when a PLD such as an FPGA (Field Programmable Gate Array) is used as a component, a circuit designer needs to create a symbol of the PLD after designing the PLD and register the symbol in a symbol library. However, the circuit designer's main practice is to design a circuit by coordinating components, so that most of circuit designers are unused to create a symbol of a component. Therefore, to create a symbol each time upon a design change of the PLD imposes a heavy burden on the circuit designer.
Consequently, there has been developed a technology for supporting a creation of a symbol of the PLD. For example, Japanese Patent Application No. Laid-open No. 2006-79447 discloses an FPGA design supporting apparatus that automatically creates an FPGA library based on information on a pin layout of an FPGA.
However, there is a problem such that the FPGA library is created by the FPGA design supporting apparatus, though, an FPGA symbol in the circuit diagram needs to be replaced each time the FPGA is changed during designing the circuit. Furthermore, in the FPGA symbol created by the FPGA design supporting apparatus, a portion dividing and a pin layout are changed due to a change of the FPGA in most cases, and thus it may be necessary to change the circuit diagram drastically.